Delay-Line Sharing Based: A New 600-MHz 16-bit Resolution CMOS DPWM Circuit
نویسندگان
چکیده
This paper presents a new circuit design for digital pulse-width modulators (DPWM). In this paper, we improve the structure of hybrid DPWM by utilization of the separation of MSB/LSB group. In addition, a delay line element is shared by MSB/LSB group to reduce the power consumption. The new DPWM prototype circuit operates at 600 MHz clock frequency and has 1.1-mW power consumption. An experimental chip is fabricating by using a standard 0.18 micron CMOS process. The layout area is 461 um × 370 um. Post-layout simulation shows the new DPWM with advantages of smaller chip area and low power consumption especially for PWM with high resolution requirement.
منابع مشابه
Hybrid DPWM with Process and Temperature Calibration
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